Accelerate Hardware Development
Arch2Code
With Arch2Code, a concept can be transformed into architecture. Represent a design as a single source of truth in a text-based YAML description.
Arch2Code reads the YAML specification and generates output suitable for various implementations. It transforms architectural objects, including Blocks, Interfaces, Memories, and Registers, into appropriate content & header files across multiple output formats:
- Documentation
- SystemVerilog
- SystemC
- C++/C Firmware
In addition, SystemVerilog code includes test bench harnesses, verification infrastructure, co-simulation, and test automation to start testing from day 1. Everything defined in the single source of truth is identical in any generation. When an architecture is updated, all generated outputs match the updated design. Safely decouple Verification and Firmware development from RTL implementation.
Arch2code eliminates an entire class of bugs common in Hardware development. Any coordination and communication of changes that cross disciplines: Architecture, RTL Design, RTL Design Verification, Software Modeling, Firmware, etc. A single architecture change is observable in all generated outputs. One repository, one source, and many generated output formats.
Fully compatible with Verilator. Run different test configurations of blocks with fully swappable RTL/SystemC from a single compile at the block level. Additionally, run mixed block tandem mode to get SW-level debugging of RTL for rapid turnaround of hardware bugs.
